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showing 10 items of 11291 documents
Latvijas Vēstures Institūta Žurnāls. 2012, Nr. 2 (83)
2012
Valsts pētījuma programma "Nacionālā identitāte: valoda, Latvijas vēsture, kultūra un cilvēkdrošība"
Kulinaria w przestrzeni miasta : nowe trendy, nowe potrzeby mieszkańców
2015
The subject of this article is culinary trends observable in Polish cities during the past few years. They include both the rediscovered practices, directly related to the cultural (culinary) heritage of a particular area, and these which have become popular only recently. According to the author, characteristic culinary fads are: the promotion of local delicacies on a large scale, growing interest in shopping in farmers’ markets offering organic produce (bio-markets) and traditional goods, growing popularity of street food (including street food festivals and picnics), and organizing the so called “breakfast on the grass” events.
Circular RNA in Exosomes
2018
Circular RNAs (circRNAs) are a novel family of non-coding endogenous RNAs discovered in all eukaryotic cells and generated through a particular mechanism of alternative splicing called “back-splicing”. These molecules show multiple functions, by acting as modulators of gene and miRNA expression, and may have a role in several biological processes, such as cell proliferation and invasion with, tumour development and progression, and in several mechanisms underlying other diseases. Their presence has been shown to be abundant in several body fluids such as blood and saliva. Based on their biogenesis mechanism, cir- cRNAs may be categorized into five classes: exonic circRNAs, intronic circRNAs…
Due note etimologiche circostanziali circa il Ms.II.D.54 (BNN) attribuito a Baffi
2019
Within the investigations on the attribution of some manuscripts to the famous philologist P. Baffi and now kept at the National Library of Naples (BNN), this brief contribution investigates in detail some of the passages contained in Ms.II.D.54 (f. 234r et f. 325r), in order to understand its meaning and to evaluate and validate its attributing hypotheses.
Statistics-preserving bijections between classical and cyclic permutations
2012
Recently, Elizalde (2011) [2] has presented a bijection between the set C"n"+"1 of cyclic permutations on {1,2,...,n+1} and the set of permutations on {1,2,...,n} that preserves the descent set of the first n entries and the set of weak excedances. In this paper, we construct a bijection from C"n"+"1 to S"n that preserves the weak excedance set and that transfers quasi-fixed points into fixed points and left-to-right maxima into themselves. This induces a bijection from the set D"n of derangements to the set C"n"+"1^q of cycles without quasi-fixed points that preserves the weak excedance set. Moreover, we exhibit a kind of discrete continuity between C"n"+"1 and S"n that preserves at each s…
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT
2012
International audience; This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a Model-Driven Engineering (MDE) methodology, which exploits two widely used standards for Systems-on-Chip specification, MARTE and IP-XACT. The presented work deals with the deployment level of the MDE approach, in which the abstract components of the platform are first linked to the lower level IP-XACT counterparts. At this phase, information for parameterization and integration is readily available, and a synthesizable model can be obtained from the gener…
A fully-digital realtime SoC FPGA based phase noise analyzer with cross-correlation
2017
We report on a fully-digital and realtime operation of a phase noise analyzer using modern digital techniques with cross-correlation. With the advent of system on chip field-programmable gate arrays (SoC FPGAs) embedding hard core central processing unit, coprocessor and FPGA onto a single integrated circuit, the building of sensitive analysis devices for Time & Frequency research is made accessible at virtually no cost and benefits from reconfigurability. Used with high-speed digitizers we have successfully implemented a four-channel system whose preliminary results at 10 MHz shows a residual white noise floor < −185 dBrad2/Hz up to 5 MHz off the carrier, and flicker < −127 dBrad2/Hz using…
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture
2019
In this paper, we propose a two-step fault-tolerant approach to address the faults occurred in cores. In the first stage, a Particle Swarm Optimization (PSO) based approach has been proposed for the fault-tolerant mapping of multiple applications on to the mesh based reconfigurable architecture by introducing spare cores and a heuristic has been proposed for the reconfiguration in the second stage. The proposed approach has been experimented by taking several benchmark applications into consideration. Communication cost comparisons have been carried out by taking the failed cores as user input and the experimental results show that our approach could get improvements in terms of communicati…
Two prospective Li-based half-Heusler alloys for spintronic applications based on structural stability and spin–orbit effect
2017
To search for half-metallic materials for spintronic applications, instead of using an expensive trial-and-error experimental scheme, it is more efficient to use first-principles calculations to design materials first, and then grow them. In particular, using a priori information of the structural stability and the effect of the spin–orbit interaction (SOI) enables experimentalists to focus on favorable properties that make growing half-metals easier. We suggest that using acoustic phonon spectra is the best way to address the stability of promising half-metallic materials. Additionally, by carrying out accurate first-principles calculations, we propose two criteria for neglecting the SOI s…
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
2010
The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…